One type of modern nonvolatile memory is the EPROM or EEPROM device that uses a floating gate structure. The memory cells within these devices use channel hot electrons for programming from the drain side and use Fowler-Nordheim tunneling for erasure from the source side. The gate structure for these devices is typically a stack configuration comprising a floating gate and a control gate separated by an insulator layer.
The formation of the stacked gate structure involves the deposition and patterning of two separate conductive layers. The inner layer is used to form the floating gate structures and is patterned so that each floating gate structure for each cell is separated from adjacent cells. The outward conductive layer forms the control gate and is typically used to connect adjacent cells to form a word line. The sequence of etch steps which are used to isolate the floating gate structures can sometimes result in the inadvertent etching of other semiconductor surfaces within the memory array. These processes can result in the formation of holes or trenches in areas of the semiconductor substrate where such features are not desired. For example, an unwanted hole or trench in the connected source region within a memory array can make it difficult or less efficient to implant dopings within the source region to make the source region as conductive as possible.
Accordingly, a need has arisen for a processing method which provides for the formation of the stacked gate structure for use in the floating gate memory array, but which does not produce unwanted holes or trenches in other portions of the array.